In the fabrication of semiconductor devices, such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on semiconductor wafers. The wafers include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnected metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
During the series of manufacturing operations, the wafer surface is exposed to various types of contaminants. Essentially, any material present in a manufacturing operation is a potential source of contamination. For example, sources of contamination may include process gases, chemicals, deposition materials, and liquids, among others. The various contaminants may deposit on the surface of a wafer as particulate matter. If the particulate contamination is not removed, the devices within the vicinity of the contamination will likely be inoperable. Thus, it is necessary to clean contamination from the wafer surface in a substantially complete manner without damaging the features defined on the wafer. The size of particulate contamination is often on the order of critical dimension size of the features being fabricated on the wafer. Removal of such small particulate contamination without adversely affecting the features on the wafer can be a challenge.
Conventional wafer cleaning methods have relied heavily on mechanical force to remove particulate contamination from the wafer. As feature size continues to decrease and become more fragile, the probability of feature damage due to application of mechanical force to the wafer surface increases. For example, features having high aspect ratios are vulnerable to toppling or breaking when impacted by a sufficient mechanical force. To further complicate the cleaning problem, the move toward reduced feature sizes also causes a reduction in the size of particulate contamination that may cause damage. Particulate contamination of sufficiently small size can find its way into difficult-to-reach areas on the wafer surface, such as in a trench surrounded by high-aspect ratio features or bridging of conductive lines, etc. Thus, efficient and non-damaging removal of contaminants during marred and semiconductor fabrication represents continuous challenge to be met by continuing advances in wafer cleaning technology. It should be appreciated that the manufacturing operations for flat panel displays suffer from the same shortcomings of the integrated circuit manufacturing discussed above. Thus, any technology requiring contaminant removal is in need of a more effective and less-abrasive cleaning technique.